The invention relates to reserving space for expansion cards.
As shown in FIGS. 50A-B, when a computer system 1203 having a Peripheral Component Interconnect (PCI) bus architecture first powers up, a central processing unit (CPU) 1207 locates PCI buses 1217 and PCI devices (e.g., PCI--PCI bridge circuits 1215) of the computer system 1203 and determines the type of each PCI device. The PCI device is non-responsive to memory space and input/output (I/O) space addressing on its PCI bus 1217 until the configuration space of the PCI device is programmed by the CPU 1207 through configuration cycles which use a PCI device identifier set for addressing the PCI device.
The PCI device identifier set uniquely identifies each PCI device and includes a unique integer bus number (identifying the PCI bus 1217 to which the PCI device is connected) and an integer device number. The device numbers are unique for PCI devices coupled to a common PCI bus 1217. The PCI device identifier set further includes an integer function number used to address PCI functions of the PCI device.
The CPU 1207 locates PCI buses 1217 and devices at power up by scanning, or "walking," the computer system 1203. The CPU 1207 assigns the unique bus number to each PCI bus 1217 that is found during the scanning of the computer system 1203. The CPU 1207 allocates memory and I/O space for each PCI device and, using the configuration cycles, programs the configuration space of each PCI device with the addresses of the memory and I/O space allocated for the PCI device. After the configuration cycles are completed, each PCI device may then be assigned I/O and/or memory space, and each PCI device then responds to memory space and I/O space bus cycles accordingly.
The numbering of the PCI buses 1217 forms a hierarchical tree 1205. The primary PCI bus 1217a, the one located closest to the CPU 1207, is typically assigned bus number zero. A PCI bus 1217 that is located downstream of (farther from the CPU 1207, as measured by PCI--PCI bridge circuits 1215, than) another PCI bus 1217 must have a higher bus number than the PCI bus 1217 that is located upstream (closer to the CPU 1207, as measured by PCI--PCI bridge circuits 1215).